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description the CXP847P60 is a cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time base timer, capture timer/counter, frc capture unit, high- precision timing pattern generation circuit, pwm output, and the like besides the basic configurations of 8-bit cpu, prom, ram, and i/o ports. the CXP847P60 also provides the sleep/stop functions that enable to execute the power-on reset function and lower the power consumption. the CXP847P60 is the prom-incorporated version of the cxp84716/84720/84724 with built-in mask rom. this provides the additional feature of being able to write directly into the program. thus, it is most suitable for evaluaiton use during system development and for small-quantity production. features a wide instruction set (213 instructions) which covers various types of data. ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 250ns at 16mhz operation (4.5 to 5.5v) 333ns at 12mhz operation (3.0 to 5.5v) incorporated prom capacity 60k bytes incorporated ram capacity 2144 bytes peripheral functions ?a/d converter 8 bits, 8 channels, successive approximation method (conversion time of 1.6s at 16mhz) ?serial interface srart-stop synchronization (uart), 1 channel incorporated buffer ram (auto transfer for 1 to 32 bytes), 2 channels 8-bit clock syncronization (msb/lsb first selectable), 1 channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter ?frc capture unit incorporated 24-bit and 6-stage fifo ?high-precision timing pattern generation circuit ppg: maximum of 11 pins, 16 stages programmable, 2 channels ?pwm output 8 bits, 8 channels interruption 19 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp/lqfp structure silicon gate cmos ic ?1 CXP847P60 e97119-ps cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (plastic) 100 pin lqfp (plastic)
?2 CXP847P60 ram 2144 bytes spc 700 cpu core interrupt controller a/d converter int3 int1 int0 int2 an0 to an7 8 rst v dd v ss extal xtal av ref av ss rxd txd prom 60k bytes 2 clock generator/ system control port a 6 2 pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe5 pe6 to pe7 pf0 to pf5 pg0 to pg7 pi0 to pi7 port b port c port d port e port f port g port i ph0 to ph7 port h uart receiver uart transmitter uart baud rate generator 8 8 8 8 6 8 8 8 nmi int4 nmi 2 pwm0 8 bit pwm generator 0 8 bit pwm generator 1 pwm1 serial interface unit (ch0) buffer ram cs0 si0 so0 sck0 serial interface unit (ch1) 16 bit capture timer/counter 2 to 8 bit timer/counter 0 8 bit timer 1 ec0 cint ec1 serial interface unit (ch2) si2 so2 sck2 pf6 pj0 to pj7 port j 8 av dd 8 bit pwm generator 2 pwm2 8 bit pwm generator 3 pwm3 8 bit pwm generator 4 pwm4 8 bit pwm generator 5 pwm5 8 bit pwm generator 6 pwm6 8 bit pwm generator 7 pwm7 cs1 si1 so1 sck1 pf7 buffer ram programmable pattern generator (ch1) prescaler/ time base timer frc capture unit fifo 11 11 4 buffer ram programmable pattern generator (ch0) ppo0 to ppo10 ppo11 to ppo21 exi0 to exi3 buffer ram block diagram
?3 CXP847P60 pin assignment (top view) 100-pin qfp package pf3 pf4 pf5 pf6/txd pf7/rxd pd0/ppo0 pd1/ppo1 pd2/ppo2 pd3/ppo3 pd4/ppo4 pd5/ppo5 pd6/ppo6 pd7/ppo7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0/ppo8 ph1/ppo9 ph2/ppo10 ph3/ppo11 ph4/ppo12 ph5/ppo13 ph6/ppo14 ph7/ppo15 pj0/ppo16 pi1/int1 pi0/int0 pe7/to pe6 pe5 pe4 pe3/nmi pe2 pe1/ec1 pe0/ec0 pb7/so1 pb6/si1 pb5/sck1 pb4/cs1 pb3 pb2 pb1 pb0/cint so0 si0 sck0 cs0 pa7 pa6 pa5 pa4 pa3/an7 pa2/an6 pa1/an5 pa0/an4 pf2 pf1 pf0 pg7/pwm7 pg6/pwm6 pg5/pwm5 pg4/pwm4 pg3/pwm3 pg2/pwm2 pg1/pwm1 vpp v dd v ss pg0/pwm0 pi7/so2 pi6/si2 pi5/sck2 pi4/int4 pi3/int3 pi2/int2 pj1/ppo17 pj2/ppo18 pj3/ppo19 pj4/ppo20 pj5/ppo21 pj6/exi0 pj7/exi1 rst extal xtal v ss exi2 exi3 av ss av ref av dd an0 an1 an2 an3 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 note) 1. vpp (pin 90) is left open. 2. v ss (pins 41 and 88) are both connected to gnd.
?4 CXP847P60 pf5 pf6/txd pf7/rxd pd0/ppo0 pd1/ppo1 pd2/ppo2 pd3/ppo3 pd4/ppo4 pd5/ppo5 pd6/ppo6 pd7/ppo7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0/ppo8 ph1/ppo9 ph2/ppo10 ph3/ppo11 ph4/ppo12 ph5/ppo13 pe6 pe5 pe4 pe3/nmi pe2 pe1/ec1 pe0/ec0 pb7/so1 pb6/si1 pb5/sck1 pb4/cs1 pb3 pb2 pb1 pb0/cint so0 si0 sck0 cs0 pa7 pa6 pa5 pa4 pa3/an7 pa2/an6 pf4 pf3 pf2 pf1 pf0 pg7/pwm7 pg6/pwm6 pg5/pwm5 pg4/pwm4 pg3/pwm3 pg2/pwm2 pg1/pwm1 vpp v dd v ss pg0/pwm0 pi7/so2 pi6/si2 pi5/sck2 pi4/int4 pi3/int3 pi2/int2 pi1/int1 pi0/int0 pe7/to ph6/ppo14 ph7/ppo15 pj0/ppo16 pj1/ppo17 pj2/ppo18 pj3/ppo19 pj4/ppo20 pj5/ppo21 pj6/exi0 pj7/exi1 rst extal xtal v ss exi2 exi3 av ss av ref av dd an0 an1 an2 an3 pa0/an4 pa1/an5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 76 77 78 79 80 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 pin assignment (top view) 100-pin lqfp package note) 1. vpp (pin 88) is left open. 2. v ss (pins 39 and 86) are both connected to gnd.
?5 CXP847P60 analog inputs to a/d converter. (4 pins) (port a) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (port b) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. can drive 12ma sink current. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. data is gated with ppo contents by or-gate and they are output. (8 pins) (port e) 8-bit port. lower 6 bits are for input; upper 2 bits are for output. (8 pins) pin description an0 to an3 pa0/an4 to pa3/an7 pa4 to pa7 pb0/cint pb1 to pb3 pb4/cs1 pb5/sck1 pb6/si1 pb7/so1 pc0 to pc7 pd0/ppo0 to pd7/ppo7 pe0/ec0 pe1/ec1 pe2 pe3/nmi pe4 to pe5 pe6 pe7/to input i/o/input i/o i/o/input i/o i/o/input i/o/i/o i/o/input i/o/output i/o i/o/real-time output input/input input/input input input/input input output output/output analog inputs to a/d converter. (4 pins) external capture input to 16-bit timer/counter. chip select input for serial interface (ch1). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1). ppo0 to ppo7 outputs for programmable pattern generator (ppg0). functions as high-precision real-time pulse output port. (ppg0: 11 pins; ppg1: 11 pins) external event inputs for timer/counter. (2 pins) non-maskable interruption request. rectangular wave output for 16-bit timer/counter. symbol i/o description
?6 CXP847P60 (port f) lower 6 bits are for i/o. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits (pf0 to pf3) or 2 bits (pf4, pf5). pf6 is for output; pf7 is for input. (8 pins) (port g) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (port h) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. data is gated with ppo contents by or-gate and they are output. (8 pins) (port i) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (port j) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. data is gated with ppo contents by or-gate and they are output. (8 pins) external inputs to frc capture unit. (2 pins) chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). pf0 to pf5 pf6/txd pf7/rxd pg0/pwm0 to pg7/pwm7 ph0/ppo8 to ph7/ppo15 pi0/int0 to pi4/int4 pi5/sck2 pi6/si2 pi7/so2 pj0/ppo16 to pj5/ppo21 pj6/exi0 pj7/exi1 exi2 to exi3 cs0 sck0 si0 so1 i/o output/output input/input i/o/output i/o/real-time output i/o/input i/o/i/o i/o/input i/o/output i/o/real-time output i/o/input i/o/input input input i/o input output uart transmission data output. uart reception data input. pwm outputs. (8 pins) ppo8 to ppo11 (ppg0) outputs and ppo12 to ppo15 (ppg1) outputs for programmable pattern generator (ppg0, ppg1). functions as high-precision real-time pulse output port. external interruption request inputs. (5 pins) serial clock i/o (ch2). serial data input (ch2). serial data output (ch2). ppo16 to ppo21 outputs for programmable pattern generator (ppg1). functions as high-precision real-time pulse output port. external inputs to frc capture unit. (2 pins) symbol i/o description
?7 CXP847P60 connects a crystal for system clock oscillation. when a clock is supplied externally, input it to extal pin and input a reversed phase clock to xtal pin. system reset; active at low level. this pin is i/o pin, and outputs low level at the power on with the power-on reset function executed. (mask option) positive power supply for incorporated prom writing. leave this pin open for normal operation. (internally connected to v dd .) positive power supply of a/d converter. reference voltage input of a/d converter. gnd of a/d converter. positive power supply. gnd. symbol extal xtal rst vpp av dd av ref av ss v dd v ss input output i/o input i/o description
?8 CXP847P60 port b data bus rd (ports b, i, j) aaaa aaaa aa aa ports b, i, j direction ip aa aa aaaa ports b, i, j data aaaa aaaa pull-up resistor "0" when reset "0" when reset * schmitt input cint cs1 si1 si2 exi0 exi1 * pull-up transistors approx. 100k w (v dd = 4.5 to 5.5v) approx. 300k w (v dd = 3.0 to 3.6v) 4 pins hi-z hi-z when reset pa0/an4 to pa3/an7 pb0/cint pb4/cs1 pb6/si1 pi6/si2 pj6/exi0 pj7/exi1 6 pins data bus rd (port a) aaa aaa aa aa port a direction ip aa aa aaa port a data aaa aaa pull-up resistor aaa aaa port a function selection input protection circuit "0" when reset "0" when reset "0" when reset input multiplexer a/d converter * pull-up transistors approx. 100k w (v dd = 4.5 to 5.5v) approx. 300k w (v dd = 3.0 to 3.6v) * i/o circuit format for pins port a pin circuit format port i port j 13 pins hi-z pa4 to pa7 pb1 to pb3 pf0 to pf5 data bus rd (ports a, b, f) aa aa ip aa aa aaaaa ports a, b, f data "0" when reset * pull-up transistors approx. 100k w (v dd = 4.5 to 5.5v) approx. 300k w (v dd = 3.0 to 3.6v) * aaaaa aaaaa ports a, b, f direction aaaa aaaa pull-up resistor "0" when reset port a port b port f
data bus rd (ports b, i) aa ip aa aa aaaa ports b, i function selection "0" when reset * schmitt input sck in aaaa aaaa ports b, i data aaaa aaaa ports b, i direction "0" when reset aaaa aaaa pull-up resistor "0" when reset sck out serial clock output enable * pull-up transistors approx. 100k w (v dd = 4.5 to 5.5v) approx. 300k w (v dd = 3.0 to 3.6v) ?9 CXP847P60 port b 2 pins hi-z pb5/sck1 pi5/sck2 port i 2 pins hi-z pb7/so1 pi7/so2 pc0 to pc7 8 pins data bus rd (port c) aaa aaa aa aa port c direction ip aa aa aaa port c data aaa aaa pull-up resistor "0" when reset "0" when reset * 1 large current 12ma * 2 pull-up transistors approx. 100k w (v dd = 4.5 to 5.5v) approx. 300k w (v dd = 3.0 to 3.6v) * 2 * 1 data bus rd (ports b, i) aa ip aa aa aaaa aaaa ports b, i function selection "0" when reset * aaaa aaaa ports b, i data aaaa aaaa ports b, i direction "0" when reset aaaa pull-up resistor so serial data output enable "0" when reset * pull-up transistors approx. 100k w (v dd = 4.5 to 5.5v) approx. 300k w (v dd = 3.0 to 3.6v) port b port c port i hi-z when reset pin circuit format
?10 CXP847P60 hi-z pd0/ppo0 to pd7/ppo7 ph0/ppo8 to ph7/ppo15 pj0/ppo16 to pj5/ppo21 22 pins data bus rd (ports d, h, j) aaaa aaaa a a ports d, h, j direction ip a aaaa ports d, h, j data aaaa aaaa pull-up resistor "0" when reset "0" when reset * ppo data * pull-up transistors approx. 100k w (v dd = 4.5 to 5.5v) approx. 300k w (v dd = 3.0 to 3.6v) port d port h port j 7 pins hi-z pe0/ec0 pe1/ec1 pe2 pe3/nmi pe4 pe5 pf7/rxd a ip a schmitt input (inverter input for pe2, pe4, pe5) rd (ports e, f) data bus ec0, ec1, nmi, rxd port e 1 pin high level pe6 data bus rd (port e) aa aa aaaa aaaa port e data "1" when reset port e port f 1 pin pe7/to aa aa aaaa aaaa port e data aaaaa aaaaa port e function selection (lower) "00" when reset aaaaa port e function selection (upper) to to output enable 01 00 mpx internal reset signal * "1" when reset * pull-up transistors approx. 150k w (v dd = 4.5 to 5.5v) approx. 400k w (v dd = 3.0 to 3.6v) high level with the resistor of pull- up transistor on for reset ( ) port e when reset pin circuit format
?11 CXP847P60 pf6/txd a aaaaa aaaaa control for transmission and ports "0" when reset uart transmission circuit data bus rd (port f) aaaa aaaa port f data "1" when reset high level 1 pin port f 8 pins pg0/pwm0 to pg7/pwm7 data bus rd (port g) aa ip aa aa aaaa port g function selection "0" when reset * aaaa aaaa port g data aaaa aaaa port g direction "0" when reset aaaa pull-up resistor pwm "0" when reset * pull-up transistors approx. 100k w (v dd = 4.5 to 5.5v) approx. 300k w (v dd = 3.0 to 3.6v) port g hi-z 5 pins hi-z data bus rd (port i) aa aa ip aa aa aaaa port i data "0" when reset * aaaa aaaa port i direction aaaa aaaa pull-up resistor "0" when reset int0 int1 int2 int3 int4 schmitt input * pull-up transistors approx. 100k w (v dd = 4.5 to 5.5v) approx. 300k w (v dd = 3.0 to 3.6v) port i pi0/int0 to pi4/int4 hi-z an0 to an3 aa aa aa aa ip a/d converter input multiplexer 4 pins when reset pin circuit format
?12 CXP847P60 2 pins hi-z exi2 exi3 a ip aa aa schmitt input exi2, exi3 so0 output enable aa aa so0 from sio 1 pin hi-z hi-z cs0 si0 aa aa aa ip schmitt input sio 2 pins so0 1 pin high level sck0 sck0 output enable aa aa internal serial clock from sio aa aa ip schmitt input external serial clock to sio 2 pins extal xtal aa aa ip aa extal xtal a ip ?diagram shows the circuit composition during oscillation. ?feedback resistor is removed during stop mode and xtal becomes high level. 1 pin low level (during a reset) rst a a schmitt input pull-up resistor mask option op aa ip from power-on reset circuit (mask option) see the selection guide for the mask option. oscillation when reset pin circuit format
?13 CXP847P60 supply voltage input voltagte output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation * 1 av dd and v dd must be set to the same voltage. * 2 v in and v out must not exceed v dd + 0.3v. * 3 the large current output pins are port c (pc). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. v dd vpp av dd av ss av ref v in v out i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 ?.3 to +13.0 av ss to +7.0 * 1 ?.3 to +0.3 av ss to +7.0 ?.3 to +7.0 * 2 ?.3 to +7.0 * 2 ? ?0 15 20 100 ?0 to +75 ?5 to +150 600 380 v v v v v v v ma ma ma ma ma ? ? mw incorporated prom output (value per pin) total for all output pins all pins excluding large current outputs (value per pin) large current outputs (value per pin) * 3 total for all output pins qfp package lqfp package item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
?14 CXP847P60 high level input voltage low level input voltage operating temperature supply voltage analog voltage 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 v dd + 0.2 0.3v dd 0.2v dd 0.2v dd 0.4 0.2 +75 v v v v v v v v v v ? v v v v v item symbol min. 4.5 3.0 5.5 5.5 max. unit remarks fc = 16mhz or less guaranteed operation range for 1/2 and 1/4 frequency dividing clock. fc = 12mhz or less 2.7 2.5 3.0 0.7v dd 0.8v dd 0.8v dd v dd ?0.4 v dd ?0.2 0 0 0 ?.3 ?.3 ?0 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/16 frequency dividing clock or sleep mode guaranteed data hold range during stop mode * 1 * 2 , * 5 * 2 , * 6 hysteresis input * 3 extal pin * 4 , * 5 extal pin * 4 , * 6 * 2 , * 5 * 2 , * 6 hysteresis input * 3 extal pin * 4 , * 5 extal pin * 4 , * 6 v dd av dd * 1 av dd and v dd must be set to the same voltage. * 2 normal input port (pa, pb1 to pb3, pb7, pc, pd, pe2, pe4, pe5, pf0 to pf5, pg, ph, pi7, pj0 to pj5) * 3 rst, cint, cs0, cs1, sck0, sck1, sck2, si0, si1, si2, ec0, ec1, nmi, rxd, int0, int1, int2, int3, int4, exi0, exi1, exi2 and exi3 * 4 specifies only when the external clock is input. * 5 this case applies to the range of 4.5 to 5.5v supply voltage (v dd ). * 6 this case applies to the range of 3.0 to 5.5v supply voltage (v dd ). recommended operating conditions (vss = 0v reference)
?15 CXP847P60 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 4.5v, v il = 4.0v v dd = 5.5v v i = 0, 5.5v high level output voltage low level output voltage input current i/o leakage current 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 ?.78 v v v v v ? ? ? ? ? ? ? ? pc pa to pd, pe6, pe7, pf0 to pf6, pg to pj, sck0, so0 pa to pd, pe6, pe7, pf0 to pf6, pg to pj, sck0, so0, rst * 1 extal tex rst * 2 pa to pd * 3 , pf0 to pf 5 * 3 , pg to pj * 3 pa to pd * 3 , pe0 to pe5, pf0 to pf5 * 3 , pf7, pg to pj * 3 , cs0, sck0, si0, exi2, exi3, an0 to an3 rst * 2 0.4 0.6 1.5 40 ?0 10 ?0 ?00 ?5 ?0 dc characteristics (v dd = 4.5 to 5.5v) electrical characteristics (ta = ?0 to +75?, v ss = 0v reference) v oh v ol i ihe i ile i iht i ilt i ilr i il i iz item symbol pins conditions min. typ. max. unit
?16 CXP847P60 supply current * 4 item symbol pins conditions min. 24 50 ma ma ? 1.5 10 10 pa to pd, pe0 to pe5, pf0 to pf5, pf7, pg to pj, cs0, sck0, si0, exi2, exi3, an0 to an3, extal, rst clock 1mhz 0v for all pins excluding measured pins v dd = 5.5v, 16mhz crystal oscillation (c 1 = c 2 = 15pf) 1/2 frequency dividing clock operation v dd i dd i dds1 i dds2 c in typ. max. unit * 1 rst pin specifies the output voltage only when the power-on reset circuit is selected with mask option. * 2 rst pin specifies the input current when the pull-up resistance is selected, and specifies the leakage current when no resistance is selected. * 3 pa to pd, pf0 to pf5 and pg to pj pins specify the input current when the pull-up resistance is selected, and specify the leakage current when no resistance is selected. * 4 when all pins are open. note) see the selection guide for the mask option. v dd = 5.5v, 16mhz crystal oscillation (c 1 = c 2 = 15pf) sleep mode stop mode v dd = 5.5v, termination of 16mhz crystal oscillation input capacity pf 20 10
?17 CXP847P60 v dd = 3.0v, i oh = ?.15ma v dd = 3.0v, i oh = ?.5ma v dd = 3.0v, i ol = 1.2ma v dd = 3.0v, i ol = 1.6ma v dd = 3.0v, i ol = 5.0ma v dd = 3.6v, v ih = 3.6v v dd = 3.6v, v il = 0.3v v dd = 3.6v, v il = 3.6v v dd = 3.6v, v il = 0.4v v dd = 3.6v, v il = 0.3v v dd = 3.0v, v il = 2.7v v dd = 3.6v v i = 0, 3.6v high level output voltage low level output voltage input current i/o leakage current 2.7 2.3 0.3 ?.3 0.1 ?.1 ?.9 ?.0 v v v v v ? ? ? ? ? ? ? ? pc pa to pd, pe6, pe7, pf0 to pf6, pg to pj, sck0, so0 pa to pd, pe6, pe7, pf0 to pf6, pg to pj, sck0, so0, rst * 1 extal tex rst * 2 pa to pd * 3 , pf0 to pf 5 * 3 , pg to pj * 3 pa to pd * 3 , pe0 to pe5, pf0 to pf5 * 3 , pf7, pg to pj * 3 , cs0, sck0, si0, exi2, exi3, an0 to an3 rst * 2 0.3 0.5 1 20 ?0 10 ?0 ?00 ?0 ?0 dc characteristics (v dd = 3.0 to 3.6v) electrical characteristics (ta = ?0 to +75?, v ss = 0v reference) v oh v ol i ihe i ile i iht i ilt i ilr i il i iz item symbol pins conditions min. typ. max. unit
?18 CXP847P60 supply current * 4 item symbol pins conditions min. 10 25 ma ma ? 0.5 2.0 10 pa to pd, pe0 to pe5, pf0 to pf5, pf7, pg to pj, cs0, sck0, si0, exi2, exi3, an0 to an3, extal, rst clock 1mhz 0v for all pins excluding measured pins v dd = 3.6v, 12mhz crystal oscillation (c 1 = c 2 = 15pf) 1/2 frequency dividing clock operation v dd i dd i dds1 i dds2 c in typ. max. unit * 1 rst pin specifies the output voltage only when the power-on reset circuit is selected with mask option. * 2 rst pin specifies the input current when the pull-up resistance is selected, and specifies the leakage current when no resistance is selected. * 3 pa to pd, pf0 to pf5 and pg to pj pins specify the input current when the pull-up resistance is selected, and specify the leakage current when no resistance is selected. * 4 when all pins are open. note) see the selection guide for the mask option. v dd = 3.6v, 12mhz crystal oscillation (c 1 = c 2 = 15pf) sleep mode stop mode v dd = 3.6v, termination of 12mhz crystal oscillation input capacity pf 20 10
?19 CXP847P60 extal t xh t xl t cf t cr 0.4v (v dd = 4.5 to 5.5v) v dd ?0.4v (v dd = 4.5 to 5.5v) 1/fc v dd ?0.3v 0.3v aaaa a aa a aaaa aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 ec0 ec1 t eh t el t ef t er 0.2v dd 0.8v dd fig. 2. clock applied conditions fig. 1. clock timing fig. 3. event count clock timing ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time f c t xl t xh t cr t cf t eh t el t er t ef xtal extal xtal extal xtal extal ec0 ec1 ec0 ec1 mhz ns ns ns ms item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 1 1 28 37.5 t sys + 50 * 1 typ. max. 16 12 200 20 (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v reference) * 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (clc: 00fe h ). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1? v dd = 4.5 to 5.5v v dd = 4.5 to 5.5v
?20 CXP847P60 note 1) t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) cs, sck, si and so represent cs0, sck0, si0 and so0 for ch0; they represent cs1, sck1, si1 and so1 for ch1, respectively. note 3) the load of sck output mode and so output delay time is 50pf + 1ttl. (2) serial transfer (ch0, ch1) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) cs ? sck delay time cs - ? sck floating delay time cs ? so delay time cs - ? so floating delay time cs high level width t sys + 200 2 t sys + 200 8000/fc t sys + 100 4000/fc ?50 t sys + 100 200 2 t sys + 200 100 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 2 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns item symbol pin conditions min. max. unit chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck cycle time sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck1 sck0 sck1 so0 so1 so0 so1 cs0 cs1 sck0 sck1 sck0 sck1 si0 si1 si0 si1 so0 so1
note 1) t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) cs, sck, si and so represent cs0, sck0, si0 and so0 for ch0; they represent cs1, sck1, si1 and so1 for ch1, respectively. note 3) the load of sck output mode and so output delay time is 50pf. ?21 CXP847P60 serial transfer (ch0, ch1) (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v reference) cs ? sck delay time cs - ? sck floating delay time cs ? so delay time cs - ? so floating delay time cs high level width t sys + 200 2 t sys + 200 8000/fc t sys + 100 4000/fc ?100 t sys + 100 200 2 t sys + 200 100 1.5 t sys + 250 1.5 t sys + 200 1.5 t sys + 250 1.5 t sys + 200 2 t sys + 250 125 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns item symbol pin conditions min. max. unit chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck cycle time sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck1 sck0 sck1 so0 so1 so0 so1 cs0 cs1 sck0 sck1 sck0 sck1 si0 si1 si0 si1 so0 so1
?22 CXP847P60 fig. 4. serial transfer ch0, ch1 timing cs0 cs1 sck0 sck1 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 si1 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 so1
?23 CXP847P60 serial transfer (ch2) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pin min. max. unit conditions sck cycle time sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t kcy t kh t kl t sik t ksi t kso sck2 sck2 si2 si2 so2 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) sck, si and so represent sck2, si2 and so2 for ch2, respectively. note 3) the load of sck2 output mode and so2 output delay time is 50pf+1ttl. serial transfer (ch2) (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v reference) note 1) t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? note 2) sck, si and so represent sck2, si2 and so2 for ch2, respectively. note 3) the load of sck2 output mode and so2 output delay time is 50pf. item symbol pin min. max. unit conditions sck cycle time sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t kcy t kh t kl t sik t ksi t kso sck2 sck2 si2 si2 so2 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?100 100 200 200 100 250 125 ns ns ns ns ns ns ns ns ns ns
?24 CXP847P60 fig. 5. serial transfer ch2 timing t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd sck2 si2 so2
?25 CXP847P60 analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value convertion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian v zt * 1 v ft * 2 i ref av ref an0 to an7 ta = 25? v dd = av dd = av ref = 5.0v v ss = av ss = 0v operation mode sleep mode stop mode linearity errror zero transition voltage full-scale transition voltage resolution av ref current av ref i refs ? ? v v v av dd av dd av ref 1.0 0.7 ma 10 ? 0.6 26/f adc * 3 6/f adc * 3 av dd ?0.5 av dd ?0.3 0 item symbol pin conditions min. typ. max. unit bits (3) a/d converter characteristics (ta = ?0 to +75?, v dd = av dd = 3.0 to 5.5v, vss = av ss = 0v reference) 8 3 lsb 70 mv 5030 10 4970 ?0 4910 mv fig.6. definition of a/d converter terms linearity errror zero transition voltage full-scale transition voltage v zt * 1 v ft * 2 ta = 25? v dd = av dd = av ref = 3.3v v ss = av ss = 0v lsb mv mv ma 0.4 v dd = av dd = 4.5 to 5.5v v dd = av dd = 3.0 to 3.6v ?0 3215 6.5 3280 70 3345 ? v dd = 5.5v v dd = 3.6v * 1 v zt : value at which the digital conversion value changes from 00 h to 01 h and vice versa. * 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. * 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (adc: 00f9 h ). ps1 selected f adc = fc ps2 selected f adc = fc/2
?26 CXP847P60 0.2v dd 0.8v dd t ih t il t il t ih int0 int1 int2 int3 int4 nmi (nmi is specified only for the falling edge) t rsl 0.2v dd rst power supply rise time power supply cut-off time v dd 0.05 1 50 ms ms item symbol pin conditions min. max. unit t r t off power-on reset repetitive power-on reset (5) power-on reset * 1 (ta = ?0 to +75?, v dd = 4.5 to 5.5v, v ss = 0v reference) fig. 9. power-on reset 0.2v 4.5v t r t off v dd 0.2v turn the power on smoothly. * 1 power-on reset function is selected by the mask option. see the selection guide for the mask option. power-on reset function can be selected only for the supply voltage range of 4.5 to 5.5v. external interruption high, low level width reset input low level width int0 int1 int2 int3 int4 nmi rst 1 32/fc ? ? item symbol pin conditions min. max. unit t ih t il t rsl (4) interruption, reset input fig. 7. interruption input timing fig. 8. rst input timing (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v reference)
?27 CXP847P60 aaaa a aa a aaaa extal xtal c 1 c 2 rd (i) main clock reset pin pull-up resistor power-on reset function non-existent/existent non-existent/existent * 1 existent existent manufacturer model fc (mhz) c 1 (pf) c 2 (pf) rd ( ) circuit example river eletec co., ltd. hc-49/u03 kinseki ltd. hc-49/u (-s) 8.00 10.00 12.00 16.00 8.00 10.00 12.00 16.00 10 5 22 (15) 15 12 10 5 22 (15) 15 12 0 0 (i) (i) selection guide existent existent option item mask CXP847P60q-1- CXP847P60r-1- appendix fig. 10. recommended oscillation circuit for spc700 series * 1 power-on reset function "existent" is not selected under the using condition in the range of v dd =3.0 to 4.5v.
?28 CXP847P60 characteristics curve (reference) i dd ?supply current [ma] (100a) 3 45 6 0.1 5.0 1.0 v dd ?supply voltage [v] i dd ?supply current [ma] i dd vs. v dd (fc = 16mhz, ta = 25?, typical) 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 0 15 10 5 fc ?system clock [mhz] i dd vs. fc (v dd = 5v, ta = 25?, typical) 510 16 20 3 45 6 5.0 1.0 0.5 10.0 20.0 0 15 10 5 51015 20 1 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode stop mode 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode i dd ?supply current [ma] i dd vs. v dd (fc = 12mhz, ta = 25?, typical) i dd vs. fc (v dd = 3.3v, ta = 25?, typical) 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode fc ?system clock [mhz] v dd ?supply voltage [v] i dd ?supply current [ma] (100a) 0.1 0.05 (50a) 0.01 (10a) 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode
?29 CXP847P60 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy package structure 23.9 0.4 qfp-100p-l01 detail a m 100pin qfp (plastic) 20.0 ?0.1 + 0.4 0?to 15 0.15 ?0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 ?0.01 + 0.4 2.75 ?0.15 + 0.35 a 0.65 0.12 0.15 0.8 0.2 (16.3) * qfp100-p-1420-a 1.4g sony code eiaj code jedec code package material lead treatment lead material package weight epoxy/phenol resin solder plating 42 alloy package structure detail a lqfp-100p-l01 * qfp100-p-1414-a 100pin lqfp (plastic) 16.0 0.2 * 14.0 0.1 75 51 50 26 25 1 76 0.5 0.08 0.18 ?0.03 + 0.08 (0.22) a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (15.0) 0?to 10 0.1 0.1 0.5 0.2 100 0.1 note: dimension * ?does not include mold protrusion.

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